As an LSI (large scale integrated circuit) works at higher speed, has more number of signal pins, and works at lower voltage to mainly reduce power consumption, malfunction due to power supply noise is taken to be a more serious problem. In particular, as for an LSI classified as so-called high-end, total designing of silicon, packages and a board is becoming a mainstream. For example, it is very important to suppress power supply noise to an adequate level in a package board.
A power supply plane may receive, even when placed at a position far from a source of power supply noise, a certain level of noise from another power supply layer overlapping with the power supply plane, or the like, and depending on a shape of the power supply plane, a resonance with a frequency of the noise is occurred to amplify the noise large enough to invert a logic. For this reason, the necessity and effectiveness of a decoupling capacitor at a position far from the source of power supply noise are examined by using a method for checking, after completion of arrangement/wiring design of a board, whether or not there is any point on the power supply plane, at which power supply noise is abnormally large, through a PI (Power Integrity) simulation, EMI (Electro Magnetic Interference) simulation, or the like.
Japanese Laid Open Patent Application (JP-P2002-092059A) discloses a wiring design method of a printed wiring board, in which returning processes are eliminated. The design method of the printed wiring board executes arrangement/wiring processes by extracting a design restriction condition or a design allowable condition based on: circuit information based on product specification; NET information; an extraction condition determined in advance based on component information; or an extraction condition determined as necessary. The design method of the printed wiring board generates, by providing relaxing conditions to the arrangement/wiring process which fails to satisfy the above restriction condition or allowable condition, board data through partial design change without fundamentally reconfiguring the circuit information and arrangement/wiring.
Japanese Laid Open Patent Application (JP-P2004-192618A) discloses a layout check system that can accurately check whether a layout of PCB (Printed Circuit Board) allows a bypass capacitor on the PCB to function effectively. The layout check system checks layout data which defines a layout of a power source, a component having a power source pin and the bypass capacitor on a printed wiring board. The layout check system includes: storage means for storing the layout data including information based on which a first value and a second value are calculated, wherein the first value corresponds to impedance between the power source pin and the power source and the second value corresponds to impedance between the power source pin and the bypass capacitor; calculation means for calculating the first value and the second value based on the stored layout data; judgment means for judges whether the layout allows the bypass capacitor to function effectively by comparing the calculated first and second values in magnitude; and output means for outputting error information when the judgment means provide a negative judgment.
Japanese Laid Open Patent Application (JP-P2006-261470A) discloses a multilayer printed board capable of effectively arranging bypass capacitors in terms of the inhibition of radiation noises. The printed circuit board mounts a plurality of circuit elements. The printed circuit board includes a ground layer, a signal layer and a power supply layer for supplying power supply voltage to the circuit elements, which are laminated with each other via insulating member. A distance between a bypass capacitor and another bypass capacitor, which are arranged on the multilayer printed circuit board, is calculated based on information on the circuit elements. The bypass capacitors are arranged on the power supply layer at constant pitch in accordance with the distance.
Japanese Laid Open Patent Application (JP-P2007-234853A) discloses a method for checking effectiveness of a bypass capacitor, which can calculate, by considering switching current between plane layers as switching current between a power supply pin and a ground pin of an IC (Integrated Circuit), impedance between a power supply and a ground of the IC, between which an bypass capacitor is provided, such that the calculated impedance coincides with an measurement result. The method for checking the bypass capacitor includes: a storage step for storing design data of a printed board and information data of the IC; a calculation step for calculating, based on the stored design data, inductance H1 of a wiring from a power supply pin of the IC to a bypass capacitor, inductance H2 of a wiring from the bypass capacitor to a power supply via, inductance H3 of a wiring from a ground pin of the IC to the bypass capacitor, inductance H4 of a wiring from the bypass capacitor to a ground via, and electrostatic capacitance between a power supply plane layer and a ground plane layer; a calculation step for calculating, based on the inductance H1, the inductance H2, the inductance H3, the inductance H4, the electrostatic capacitance and the information data of the IC, a relation between impedance between the power supply pin and the ground pin of the IC and frequency of the impedance; a calculation step for calculating required impedance at an operating frequency of the IC based on the information data of the IC; and a judgment step for judging whether or not the bypass capacitor is effective by comparing the required impedance with the impedance between the power supply pin and the ground pin of the IC.